High Speed DWT Processor Implementation in FPGA

This paper presents a high speed and area efficient DWT processor VLSI based design for Image Compression applications. In this proposed design, pipelined partially serial architecture has been used to enhance the speed along with optimal utilization and resources available on the target FPGA. The architecture consists of two row processors, two column processors, and two memory modules. Each processor contains two adders, one multiplier, and one shifter. The precision of the multipliers and adders has been determined using simulation. Each memory module consists of four banks in order to support the high computational bandwidth the proposed model has been designed and simulated using Xilinx Synthesis tool (XST) target. The result comparison has shown an improvement in speed. In this compression techniques uses lifting scheme with DWT, blocking artifact and bad subjective quality are improved than in convolution method using DWT. Conventional lifting-based architectures require fewer arithmetic operations compared to the convolution-based approach for DWT. In addition to this and for the reason to preserve proper precision, intermediate variables widths are larger in lifting based computing. As a result, the lifting multiplier and adder delays are longer than the convolution ones. The main feature of the lifting based DWT scheme is to break up the high pass and low pass filters into a sequence of upper and lower triangular matrices and convert the filter implementation into banded matrix multiplications [1], [2]. Such a scheme has several advantages, including “in-place” computation of the DWT, integer-to-integer wavelet transform (IWT), symmetric forward and inverse transform, etc. The outputs generated by the row and column processors are stored in memory modules. The memory modules are divided into multiple banks to accommodate high computational bandwidth requirements. The architecture has been simulated using behavioral VHDL and the results compared with C code implementation. The lifting-based DWT architecture consisting of four processor architecture can perform transforms with one or two lifting steps one level at a time. Furthermore, the data path is pipelined, and the clock period is determined by the memory access time of performing filters with one lifting step, i.e., one predict and one update step [10]. The outputs are generated in an interleaved fashion.